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Process
: 0.13um CMOS
Reduction
of pin outs : 64-pin (6x6 64-ball FBGA, 9x9 64-lead
MLF2)
Increase
De-interleaver memory size - Supporting
Max 1.8Mbps full capacity decoding
Very
low power consumption - TCC3100 : about
35mW (544kbps DMB) - Direct RF power
down control - Total 50~70mW lower
than TCC310 RF + Base-band module
Various
external Interface - Standard serial
/ parallel TS interface - I2C repeater
Increase
of frequency compensation capability -
Integer frequency offset : ± 64KHz ”Ž ±
128KHz - Various AGC Speed
Fast
and easy TII (Transmitter Identity Information) detection
- Detection and sorting in 600ms
Small
packages - 6 x 6 64-ball FBGA -
9 x 9 64-lead ELP (QFN type)
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